9563   ins_encode( /*empty*/ );
9564   ins_pipe(pipe_class_default);
9565 %}
9566 
9567 //----------Logical Instructions-----------------------------------------------
9568 
9569 // And Instructions
9570 
9571 // Register And
9572 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9573   match(Set dst (AndI src1 src2));
9574   format %{ "AND     $dst, $src1, $src2" %}
9575   size(4);
9576   ins_encode %{
9577     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9578     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9579   %}
9580   ins_pipe(pipe_class_default);
9581 %}
9582 













9583 // Immediate And
9584 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
9585   match(Set dst (AndI src1 src2));
9586   effect(KILL cr0);
9587 
9588   format %{ "ANDI    $dst, $src1, $src2" %}
9589   size(4);
9590   ins_encode %{
9591     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9592     // FIXME: avoid andi_ ?
9593     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9594   %}
9595   ins_pipe(pipe_class_default);
9596 %}
9597 
9598 // Immediate And where the immediate is a negative power of 2.
9599 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
9600   match(Set dst (AndI src1 src2));
9601   format %{ "ANDWI   $dst, $src1, $src2" %}
9602   size(4);

9563   ins_encode( /*empty*/ );
9564   ins_pipe(pipe_class_default);
9565 %}
9566 
9567 //----------Logical Instructions-----------------------------------------------
9568 
9569 // And Instructions
9570 
9571 // Register And
9572 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9573   match(Set dst (AndI src1 src2));
9574   format %{ "AND     $dst, $src1, $src2" %}
9575   size(4);
9576   ins_encode %{
9577     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9578     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9579   %}
9580   ins_pipe(pipe_class_default);
9581 %}
9582 
9583 // Left shifted Immediate And
9584 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16  src2, flagsRegCR0 cr0) %{
9585   match(Set dst (AndI src1 src2));
9586   effect(KILL cr0);
9587   format %{ "ANDIS   $dst, $src1, $src2.hi" %}
9588   size(4);
9589   ins_encode %{
9590     // TODO: PPC port $archOpcode(ppc64Opcode_andis_);
9591     __ andis_($dst$$Register, $src1$$Register, (int)((short)(($src2$$constant & 0xFFFF0000) >> 16)));
9592   %}
9593   ins_pipe(pipe_class_default);
9594 %}
9595 
9596 // Immediate And
9597 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
9598   match(Set dst (AndI src1 src2));
9599   effect(KILL cr0);
9600 
9601   format %{ "ANDI    $dst, $src1, $src2" %}
9602   size(4);
9603   ins_encode %{
9604     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9605     // FIXME: avoid andi_ ?
9606     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9607   %}
9608   ins_pipe(pipe_class_default);
9609 %}
9610 
9611 // Immediate And where the immediate is a negative power of 2.
9612 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
9613   match(Set dst (AndI src1 src2));
9614   format %{ "ANDWI   $dst, $src1, $src2" %}
9615   size(4);